• Learn Formal Methodologies:Pick up best-in-class formal verification techniques and apply them to complex digital designs and SoCs.

• Develop Test Plans:Take ownership of verifying a design by building a robust, well-structured verification test plan.

• Execute Verification:Run the test plan in close collaboration with the design team to confirm functional correctness.

• Use Abstraction Techniques:Apply abstraction methods to make verification of large designs efficient and effective.

• Work with HDLs:Read and understand RTL written in Verilog and System Verilog quickly and accurately.

• Apply Temporal Logic:Write and reason about temporal logic assertions to capture design intent.

• Coordinate for Closure:Work with other verification team members to track, debug, and close all identified issues.